* General description
The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 or 5 V environment.
The 74LVC573A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches.
The 74LVC573A consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74LVC573A is functionally identical to the 74LVC373A, but the 74LVC373A has a different pin arrangement.
* Features
- 5 V tolerant inputs/outputs, for interfacing with 5 V logic
- Supply voltage range from 1.2 to 3.6 V
- Inputs accept voltages up to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- High impedance when VCC =0 V
- Flow-through pin-out architecture
- Complies with JEDEC standard no. 8-1A
- ESD protection:
- HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V - Specified from -40 to +85 Cel and -40 to +125 Cel.
