*Features

OMAP3530/25 Applications Processor:
  - OMAP™ 3 Architecture
  - MPU Subsystem
    - Up to 720-MHz ARM Cortex™-A8 Core
    - NEON™ SIMD Coprocessor 
  - High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
    - 520-MHz TMS320C64x+™ DSP Core
    - Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
    - Video Hardware Accelerators 
  - POWERVR SGX™ Graphics Accelerator (OMAP3530 Device Only)
    - Tile Based Architecture delivering 10 MPoly/sec
    - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex
      Shader Functionality
    - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
    - Fine Grained Task Switching, Load Balancing, and Power Management
    - Programmable High Quality Image Anti-Aliasing 
  - Fully Software-Compatible With C64x and ARM9™
  - Commercial and Extended Temperature Grades

Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
  - Eight Highly Independent Functional Units
    - +Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic
       per Clock Cycle
    - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight
       8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
  - Load-Store Architecture With Non-Aligned Support
  - 64 32-Bit General-Purpose Registers
  - Instruction Packing Reduces Code Size
  - All Instructions Conditional
  - Additional C64x+™ Enhancements
    - Protected Mode Operation
    - Exceptions Support for Error Detection and Program Redirection
    - Hardware Support for Modulo Loop Operation

C64x+ L1/L2 Memory Architecture
  - 32K-Byte L1P Program RAM/Cache (Direct Mapped)
  - 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
  - 64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative)
  - 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM

C64x+ Instruction Set Features
  - Byte-Addressable (8-/16-/32-/64-Bit Data)
  - 8-Bit Overflow Protection
  - Bit-Field Extract, Set, Clear
  - Normalization, Saturation. Bit-Counting
  - Compact 16-Bit Instructions
  - Additional Instructions to Support Complex Multiplies

ARM Cortex™-A8 Core
  - ARMv7 Architecture
    - Trust Zone®
    - Thumb®-2
    - MMU Enhancements
  - In-Order, Dual-Issue, Superscalar Microprocessor Core
  - NEON™ Multimedia Architecture
  - Over 2x Performance of ARMv6 SIMD
  - Supports Both Integer and Floating Point SIMD
  - Jazelle® RCT Execution Environment Architecture
  - Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and
     8-Entry Return Stack
  - Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug

ARM Cortex™-A8 Memory Architecture:
  - 16K-Byte Instruction Cache (4-Way Set-Associative)
  - 16K-Byte Data Cache (4-Way Set-Associative)
  - 256K-Byte L2 Cache

112K-Byte ROM

64K-Byte Shared SRAM

Endianess:
  - ARM Instructions - Little Endian
  - ARM Data — Configurable
  - DSP Instuction/Data - Little Endian

External Memory Interfaces:
  - SDRAM Controller (SDRC)
    - 16, 32-bit Memory Controller With 1G-Byte Total Address Space
    - Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
    - SDRAM Memory Scheduler (SMS) and Rotation Engine
  - General Purpose Memory Controller (GPMC)
    - 16-bit Wide Multiplexed Address/Data Bus
    - Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
    - Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM
       and Pseudo-SRAM
    - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs,
       etc.)
    - Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)

System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable
   Priority)

Camera Image Signal Processing (ISP)
  - CCD and CMOS Imager Interface 
  - Memory Data Input
  - RAW Data Interface
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - A-Law Compression and Decompression 
  - Preview Engine for Real-Time Image Processing
  - Glueless Interface to Common Video Decoders
  - Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine
  - Resize Engine
    - Resize Images From 1/4x to 4x
    - Separate horizontal/Vertical Control

Display Subsystem
  - Parallel Digital Output
    - Up to 24-Bit RGB
    - HD Maximum Resolution 
    - Supports Up to 2 LCD Panels
    - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
  - 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
    - Composite NTSC/PAL Video
    - Luma/Chroma Separate Video (S-Video)
  - Rotation 90-, 180-, and 270-degrees
  - Resize Images From 1/4x to 8x
  - Color Space Converter
  - 8-bit Alpha Blending

Serial Communication
  - 5 Multichannel Buffered Serial Ports (McBSPs)
    - 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
    - 5K-Byte Transmit/Receive Buffer (McBSP2)
    - SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations
    - Direct Interface to I2S and PCM Device and TDM Buses
    - 128 Channel Transmit/Receive Mode
  - Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
  - High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
  - High-Speed/Full-Speed/Low-Speed Multiport USB Host Controller
    - 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
    - Supports Transceiverless Link Logic (TLL)
  - One HDQ/1-Wire Interface
  - Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
  - Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers

Removable Media Interfaces:
  - Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)

Comprehensive Power, Reset, and Clock Management
  - SmartReflex™ Technology
  - Dynamic Voltage and Frequency Scaling (DVFS)

Test Interfaces
  - IEEE-1149.1 (JTAG) Boundary-Scan Compatible
  - Embedded Trace Macro Interface (ETM)
  - Serial Data Transport Interface (SDTI)

11 32-bit General Purpose Timers

2 32-bit Watchdog Timers

1 32-bit 32-kHz Sync Timer

Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)

65-nm CMOS Technology

Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS
   Package)

Descreet Memory Interface (Not Available in CBC Package)

Packages:
  - 515-pin s-PBGA Package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom)
  - 515-pin s-PBGA Package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)
  - 423-pin s-PBGA Package (CUS Suffix), .65mm Ball Pitch

1.8-V I/O and 3.0-V (MMC1 only), 0.975-V to 1.35-V Adaptive Processor Core Voltage,
  0.975-V to 1.35-V Adaptive Core Logic Voltage

Datasheet :

Delivery

1. The initial delivery day shall be the day following the day on which the product is forwarded to the delivery service.
1) Regular home-delivery (excluding order date and holidays): Seoul/Gyeonggi 3~5days, other regions 3~8days
2) Postal service: Seoul/Gyeonggi 3~5days
2. During public holidays and weekends, there will be no delivery, and any other days during which delivery is impracticable due to a force majeure event may cause delay in the delivery.
3. The buyers both within and outside of Korea shall be responsible for any delivery fee that may arise. But the products bought over 300,000 won will be delivered free of charge.

Cancellation and Refund

1. The buyer may cancel the purchase order before the product is shipped, and if the product is in the process of being delivered, transaction shall be handled pursuant to the Article 15 of products return.
2. If the product is on standby for delivery after the payment, the buyer may cancel the order at any time except for the particular circumstances.
3. If credit card has been used for the payment, the payment shall immediately be refunded as soon as the cancellation process is completed. If cash has been used for the payment, the payment shall be refunded in 5 business days via direct account transfer or others.

Return and Exchange

1. The buyer may demand a return of the product within three days after the receipt of the delivery.
2. The cost for the return delivery shall be borne by the liable party.
3. The payment of refund upon return of the product shall be completed within 5 days after the Company has received the product from the buyer.
4. The Company shall refund, return and exchange in accordance with the buyer’s demand in the following cases. Such transaction shall be processed within 10 days after the delivery.
1) Delivered product does not match with the purchase order.
2) Delivered product is lost or damaged due to the Company’s error.
3) Delivery is considerably delayed than what has been scheduled.
4) Otherwise, legitimate reasons are submitted to the Company for the demand by the buyer.

Delivery/Returned goods/Exchange Address

Guro branch : 3127, Ma-Dong, Central Distribution Complex, 1258, Guro-Dong, Guro-Gu, Seoul, Korea, 152-721
TEL : +82-2-2681-5517(REP)
FAX : +82-2-2681-5518
Support: +82-2-3397-3613
E-mail : shop@semidj.com

Overseas Delivery Service

1. The Company provides the service in accordance with the overseas delivery procedure of the products whose trade contract is already signed through the overseas delivery network that has business connection with the Company. Overseas delivery is divided into as follows:
1) A domestic delivery phase: until the buyer’s product is delivered to a logistics center of a third party in business cooperation with the Company
2) An overseas delivery phase: until the product is delivered to the recipient through the overseas delivery network
2. For overseas delivery, the buyer’s order may be cancelled depending on the status of the delivery request. Return requested due to change of mind during delivery is limited to the phase of domestic delivery. Once the product has completed the domestic delivery phase and entered the overseas delivery phase, a return is not permitted unless the Company approves return or exchange due to an original defect in the delivered product.
3. A buyer requesting the Company’s approval on return or exchange must approve the original product defect or other grounds for return or exchange by submitting to the Company objective evidence. The costs and expenses for the delivery in connection with the return or exchange shall be paid by the Company once objective evidence has been approved.
4. The buyer who has received an approval to return or exchange of the product from the Company shall contact the DJmall customer center before the return of the product, including documents to verify costs and expenses for the delivery.
5. If the estimated cost of the delivery paid at purchase is greater than the actual delivery cost, the difference will be refunded to the buyer.
6. If the estimated cost of the delivery paid at purchase is less than the actual delivery cost, the buyer must make an additional payment to complete the delivery. If the difference is not paid within 3 months despite of continuous notice, the product may become the Company’s own property.
7. In the event of using overseas delivery service, the recipient is liable for all customs, taxes, duties and other cost imposes by the country to which the delivery is made.
'BUYER IS RESPONSIBLE FOR THE DELIVERY FEE'